View CAT93C86LAT2C_4625051.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

CAT93C86 (Rev. C)
16K-Bit Microwire Serial EEPROM
FEATURES
High speed operation: 3MHz Low power CMOS technology 1.8 to 5.5 volt operation Selectable x8 or x16 memory organization Self-timed write cycle with auto-clear Hardware and software write protection Power-up inadvertant write protection Sequential read Program enable (PE) pin 1,000,000 Program/erase cycles 100 year data retention Commercial, industrial and automotive temperature ranges RoHS-compliant packages
DESCRIPTION
The CAT93C86 is a 16K-bit Serial EEPROM memory device which is configured as either registers of 16 bits (ORG pin at VCC) or 8 bits (ORG pin at GND). Each register can be written (or read) serially by using the DI (or DO) pin. The CAT93C86 is manufactured using Catalyst's advanced CMOS EEPROM floating gate technology. The device is designed to endure 1,000,000 program/erase cycles and has a data retention of 100 years. The device is available in 8-pin DIP, 8-pin SOIC and 8-pad TDFN packages.
PIN CONFIGURATION
PDIP (L) SOIC (V, X) TDFN (ZD4) CS SK DI DO 1 2 3 4 8 VCC 7 PE 6 ORG 5 GND PE VCC CS SK
FUNCTIONAL SYMBOL
VCC
SOIC (W) 1 2 3 4 8 ORG 7 GND 6 DO 5 DI
ORG CS SK PE
DI DO
GND
PIN FUNCTION (1)
Pin Name CS SK DI DO VCC GND ORG PE Function Chip Select Clock Input Serial Data Input Serial Data Output Power Supply Ground Memory Organization Program Enable For Ordering Information details, see page 12.
Notes: (1) When the ORG pin is connected to VCC, x16 organization is selected. When it is connected to ground, x8 pin is selected. If the ORG pin is left unconnected, then an internal pull-up device will select the x16 organization.
(c) 2008 SCILLC. All rights reserved Characteristics subject to change without notice
1
Doc. No. MD-1091 Rev. R
CAT93C86 (Rev. C)
ABSOLUTE MAXIMUM RATINGS (1) Parameters Temperature Under Bias Storage Temperature Voltage on any Pin with Respect to Ground(2) VCC with Respect to Ground Package Power Dissipation Capability (TA = 25C) Lead Soldering Temperature (10 seconds) Output Short Circuit Current
(3)
Ratings -55 to +125 -65 to 150 -2.0 to +VCC +2.0 -2.0 to +7.0 1.0 300 100
Units C C V V W C mA
RELIABILITY CHARACTERISTICS Symbol NEND(4) TDR(4) VZAP(4) ILTH(4)(5) Parameter Endurance Data Retention ESD Susceptibility Latch-Up Reference Test Method MIL-STD-883, Test Method 1033 MIL-STD-883, Test Method 1008 MIL-STD-883, Test Method 3015 JEDEC Standard 17 Min 1,000,000 100 2000 100 Units Cycles/Byte Years V mA
D.C. OPERATING CHARACTERISTICS VCC = +1.8V to +5.5V unless otherwise specified. Symbol ICC1 ICC2 ISB1 ISB2 ILI ILO VIL1 VIH1 VIL2 VIH2 VOL1 VOH1 VOL2 VOH2 Parameter
Power Supply Current (Write) Power Supply Current (Read) Power Supply Current (Standby) (x8 Mode) Power Supply Current (Standby) (x16Mode) Input Leakage Current Output Leakage Current (Including ORG pin) Input Low Voltage Input High Voltage Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage
Test Conditions
fSK = 1MHz; VCC = 5.0V fSK = 1MHz; VCC = 5.0V CS = 0V ORG = GND CS = 0V ORG = Float or VCC VIN = 0V to VCC VOUT = 0V to VCC, CS = 0V 4.5V VCC < 5.5V 4.5V VCC < 5.5V 1.8V VCC < 4.5V 1.8V VCC < 4.5V 4.5V VCC < 5.5V; IOL = 2.1mA 4.5V VCC < 5.5V; IOH = -400A 1.8V VCC < 4.5V; IOL = 1mA 1.8V VCC < 4.5V; IOH = -100A
Min
Typ
Max
3 500 10
Units
mA A A A A A V V V V V V V V
0
10 1 1
-0.1 2 0 VCC x 0.7 2.4
0.8 VCC + 1 VCC x 0.2 VCC + 1 0.4 0.2
VCC - 0.2
Notes: (1) Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. (2) The minimum DC input voltage is -0.5V. During transitions, inputs may undershoot to -2.0V for periods of less than 20ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20ns. (3) Output shorted for no more than one second. No more than one output shorted at a time. (4) These parameters are tested initially and after a design or process change that affects the parameter. (5) Latch-up protection is provided for stresses up to 100 mA pn address and data pins from -1V to VCC +1V.
Doc. No. MD-1091 Rev. R
2
(c) 2008 SCILLC. All rights reserved Characteristics subject to change without notice
CAT93C86 (Rev. C)
PIN CAPACITANCE (1) Symbol COUT CIN Test Output Capacitance (DO) Input Capacitance (CS, SK, DI, ORG) Conditions VOUT = 0V VIN = 0V Min Typ Max 5 5 Units pF pF
POWER-UP TIMING (1)(2) Symbol tPUR tPUW Parameter Power-up to Read Operation Power-up to Write Operation Max 1 1 Units ms ms
A.C. TEST CONDITIONS Input Rise and Fall Times Input Pulse Voltages Timing Reference Voltages Input Pulse Voltages Timing Reference Voltages A.C. CHARACTERISTICS Test Conditions VCC = 1.8V-5.5V Min 200 0 200 200 1 CL = 100pF
(3)
50ns 0.4V to 2.4V 0.8V, 2.0V 0.2VCC to 0.7VCC 0.5VCC 4.5V VCC 5.5V 4.5V VCC 5.5V 1.8V VCC 4.5V 1.8V VCC 4.5V
VCC = 2.5V-5.5V Min 100 0 100 100 0.5 0.5 200 5 0.5 0.5 0.5 Max
VCC = 4.5V-5.5V Min 50 0 50 50 0.15 0.15 100 5 0.15 0.15 0.15 Max Units ns ns ns ns s s ns ms s s s 0.1 DC 3000 s kHz
Symbol Parameter tCSS tCSH tDIS tDIH tPD1 tPD0 tHZ(1) tEW tCSMIN tSKHI tSKLOW tSV SKMAX CS Setup Time CS Hold Time DI Setup Time DI Hold Time Output Delay to 1 Output Delay to 0 Output Delay to High-Z Program/Erase Pulse Width Minimum CS Low Time Minimum SK High Time Minimum SK Low Time Output Delay to Status Valid Maximum Clock Frequency
Max
1 400 5 1 1 1 1 DC 500 DC
0.5 1000
Notes: (1) These parameters are tested initially and after a design or process change that affects the parameter. (2) (3) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. The input levels and timing reference points are shown in the "AC Test Conditions" table.
(c) 2008 SCILLC. All rights reserved Characteristics subject to change without notice
3
Doc. No. MD-1091 Rev. R
CAT93C86 (Rev. C)
INSTRUCTION SET Instruction READ ERASE WRITE EWEN EWDS ERAL WRAL Start Bit 1 1 1 1 1 1 1 Address Opcode 10 11 01 00 00 00 00 x8 A10-A0 A10-A0 A10-A0 11XXXXXXXXX 00XXXXXXXXX 10XXXXXXXXX 01XXXXXXXXX x16 A9-A0 A9-A0 A9-A0 11XXXXXXXX 00XXXXXXXX 10XXXXXXXX 01XXXXXXXX D7-D0 D15-D0 D7-D0 D15-D0 x8 Data x16 Comments Read Address AN- A0 Clear Address AN- A0 Write Address AN- A0 Write Enable Write Disable Clear All Addresses Write All Addresses
DEVICE OPERATION
The CAT93C86 is a 16,384-bit nonvolatile memory intended for use with industry standard microprocessors. The CAT93C86 can be organized as either registers of 16 bits or 8 bits. When organized as X16, seven 13-bit instructions control the reading, writing and erase operations of the device. When organized as X8, seven 14-bit instructions control the reading, writing and erase operations of the device. The CAT93C86 operates on a single power supply and will generate on chip, the high voltage required during any write operation. Instructions, addresses, and write data are clocked into the DI pin on the rising edge of the clock (SK). The DO pin is normally in a high impedance state except when reading data from the device, or when checking the ready/busy status after a write operation. The ready/busy status can be determined after the start of a write operation by selecting the device (CS high) and polling the DO pin; DO low indicates that the write operation is not completed, while DO high indicates that the device is ready for the next instruction. If necessary, the DO pin may be placed back into a high impedance state during chip select by shifting a dummy "1" into the DI pin. The DO pin will enter the high impedance state on the falling edge of the clock (SK). Placing the DO pin into the high impedance state is recommended in applications where the DI pin and the DO pin are to be tied together to form a common DI/O pin. The format for all instructions sent to the device is a logical "1" start bit, a 2-bit (or 4-bit) opcode, 10-bit address (an additional bit when organized X8) and for write operations a 16-bit data field (8-bit for X8 organizations). Note: The Write, Erase, Write all and Erase all instructions require PE=1. If PE is left floating, 93C86 is in Program Enabled mode. For Write Enable and Write Disable instruction PE = don't care. Read Upon receiving a READ command and an address (clocked into the DI pin), the DO pin of the CAT93C86 will come out of the high impedance state and, after sending an initial dummy zero bit, will begin shifting out the data addressed (MSB first). The output data bits will toggle on the rising edge of the SK clock and are stable after the specified time delay (tPD0 or tPD1). After the initial data word has been shifted out and CS remains asserted with the SK clock continuing to toggle, the device will automatically increment to the next address and shift out the next data word in a sequential READ mode. As long as CS is continuously asserted and SK continues to toggle, the device will keep incrementing to the next address automatically until it reaches to the end of the address space, then loops back to address 0. In the sequential READ mode, only the initial data word is preceeded by a dummy zero bit. All subsequent data words will follow without a dummy zero bit. Write After receiving a WRITE command, address and the data, the CS (Chip Select) pin must be deselected for a minimum of tCSMIN. The falling edge of CS will start the self clocking clear and data store cycle of the memory location specified in the instruction. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the CAT93C86 can be determined by selecting the device and polling the DO pin. Since this device features Auto-Clear before write, it is NOT necessary to erase a memory location before it is written into.
Doc. No. MD-1091 Rev. R
4
(c) 2008 SCILLC. All rights reserved Characteristics subject to change without notice
CAT93C86 (Rev. C)
tSKHI SK tDIS DI tCSS CS tDIS DO tPD0,tPD1 DATA VALID tCSMIN VALID VALID tDIH tSKLOW tCSH
Figure 1. Sychronous Data Timing
SK 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CS Don't Care AN DI 1 1 0 A--1 A0
DO
HIGH-Z
Dummy 0
D15 . . . D0 or D7 . . . D0
Address + 1 D15 . . . D0 or D7 . . . D0
Address + 2 D15 . . . D0 or D7 . . . D0
Address + n D15 . . . or D7 . . .
Figure 2. Read Instruction Timing
SK tCSMIN CS AN DI 1 0 1 tSV DO HIGH-Z tEW BUSY READY HIGH-Z tHZ AN-1 A0 DN D0 STATUS VERIFY STANDBY
Figure 3. Write Instruction Timing
(c) 2008 SCILLC. All rights reserved Characteristics subject to change without notice
5
Doc. No. MD-1091 Rev. R
CAT93C86 (Rev. C)
Erase Upon receiving an ERASE command and address, the CS (Chip Select) pin must be deasserted for a minimum of tCSMIN. The falling edge of CS will start the self clocking clear cycle of the selected memory location. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the CAT93C86 can be determined by selecting the device and polling the DO pin. Once cleared, the content of a cleared location returns to a logical "1" state. Erase/Write Enable and Disable The CAT93C86 powers up in the write disable state. Any writing after power-up or after an EWDS (write disable) instruction must first be preceded by the EWEN (write enable) instruction. Once the write instruction is enabled, it will remain enabled until power to the device is removed, or the EWDS instruction is sent. The EWDS instruction can be used to disable all CAT93C86 write and clear instructions, and will prevent any accidental writing or clearing of the device. Data can be read normally from the device regardless of the write enable/disable status. Erase All Upon receiving an ERAL command, the CS (Chip Select) pin must be deselected for a minimum of tCSMIN. The falling edge of CS will start the self clocking clear cycle of all memory locations in the device. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the CAT93C86 can be determined by selecting the device and polling the DO pin. Once cleared, the contents of all memory bits return to a logical "1" state. Write All Upon receiving a WRAL command and data, the CS (Chip Select) pin must be deselected for a minimum of tCSMIN. The falling edge of CS will start the self clocking data write to all memory locations in the device. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the CAT93C86 can be determined by selecting the device and polling the DO pin. It is not necessary for all memory locations to be cleared before the WRAL command is executed.
SK
CS AN DI 1 1 1 tSV HIGH-Z DO AN-1 A0
STATUS VERIFY tCS
STANDBY
tHZ BUSY tEW READY HIGH-Z
Figure 4. Erase Instruction Timing
Doc. No. MD-1091 Rev. R
6
(c) 2008 SCILLC. All rights reserved Characteristics subject to change without notice
CAT93C86 (Rev. C) PACKAGE OUTLINE DRAWINGS
PDIP 8-Lead 300mils (L) (1)(2)
SYMBOL
MIN
NOM
MAX
A A1 A2 b
E1
5.33 0.38 2.92 0.36 1.14 0.20 9.02 7.62 6.10 7.87 2.92 3.30 3.30 0.46 1.52 0.25 9.27 7.87 2.54 BSC 6.35 7.11 10.92 3.80 4.95 0.56 1.78 0.36 10.16 8.25
b2 c D E e E1 eB
PIN # 1 IDENTIFICATION D
L
TOP VIEW
E
A
A2
A1 b2 L c
e
b
eB
SIDE VIEW
END VIEW
For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf.
Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC standard MS-001.
(c) 2008 SCILLC. All rights reserved Characteristics subject to change without notice
7
Doc. No. MD-1091 Rev. R
CAT93C86 (Rev. C)
SOIC 8-Lead 150mils (V) (1)(2)
SYMBOL
MIN
NOM
MAX
A A1 b c
E1 E
1.35 0.10 0.33 0.19 4.80 5.80 3.80 1.27 BSC 0.25 0.40 0
1.75 0.25 0.51 0.25 5.00 6.20 4.00 0.50 1.27 8
D E E1 e h L
PIN # 1 IDENTIFICATION TOP VIEW
D
h
A1
A
c e b L
SIDE VIEW
END VIEW
For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf.
Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC standard MS-012.
Doc. No. MD-1091 Rev. R
8
(c) 2008 SCILLC. All rights reserved Characteristics subject to change without notice
CAT93C86 (Rev. C)
SOIC 8-Lead EIAJ 208mils (X) (1)(2)
SYMBOL
MIN
NOM
MAX
A A1 b c
E1 E
2.03 0.05 0.36 0.19 5.13 7.75 5.13 1.27 BSC 0.51 0 0.76 8 0.25 0.48 0.25 5.33 8.26 5.38
D E E1 e L
PIN#1 IDENTIFICATION
TOP VIEW
D
A
e
b
A1
L
c END VIEW
SIDE VIEW
For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf.
Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with EIAJ standard EDR-7320.
(c) 2008 SCILLC. All rights reserved Characteristics subject to change without notice
9
Doc. No. MD-1091 Rev. R
CAT93C86 (Rev. C)
TDFN 8-Pad 3 x 3mm (ZD4) (1)(2)
D
A
e
b L
E
E2
PIN#1 ID
PIN#1 INDEX AREA
A1
D2
TOP VIEW
SIDE VIEW
BOTTOM VIEW
SYMBOL
MIN
NOM
MAX
A A1 A3 b D D2 E E2 e L
0.70 0.00 0.23 2.90 2.20 2.90 1.40 0.20
0.75 0.02 0.20 REF 0.30 3.00 -- 3.00 -- 0.65 TYP 0.30
0.80 0.05
A A3 A1
0.37 3.10 2.50 3.10 1.80 0.40
FRONT VIEW
For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf.
Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC standard MO-229.
Doc. No. MD-1091 Rev. R
10
(c) 2008 SCILLC. All rights reserved Characteristics subject to change without notice
CAT93C86 (Rev. C) EXAMPLE OF ORDERING INFORMATION(1)
Prefix CAT
Company ID Product Number
Device # Suffix 93C86 V I
Temperature Range I = Industrial (-40C - 85C) A = Automotive (-40C - 105C) E = Extended (-40C to + 125C) Operating Voltage Blank (VCC = 2.5V to 5.5V) 1.8 (VCC = 1.8V to 5.5V)
-1.8
-G
T3
Rev C (4)
Die Revision
93C86: C
Tape & Reel T: Tape & Reel 2: 2,000/Reel(5) 3: 3,000/Reel
93C86
Package = PDIP = SOIC, JEDEC = SOIC, JEDEC (5) = SOIC, EIAJ = TDFN (3x3mm)
L V W X ZD4
Lead Finish Blank: Matte-Tin G: NiPdAu
For Product Top Mark Codes, click here: http://www.catsemi.com/techsupport/producttopmark.asp
Notes: (1) All packages are RoHS-compliant (Lead-free, Halogen-free). (2) (3) (4) (5) (6) The standard lead finish is NiPdAu. The device used in the above example is a 93C86VI-GT3 (SOIC, Industrial Temperature, 1.8V to 5.5V, NiPdAu, Tape & Reel, 3,000/Reel) Product die revision letter is marked on top of the package as a suffix to the production date code (e.g., AYWWE.) For additional information, please contact your ON Semiconductor sales office. For SOIC, EIAJ (X) package the standard lead finish is Matte-Tin. This package is available in 2,000/Reel, i.e., CAT93C86XI-T2. For additional package and temperature options, please contact your nearest ON Semiconductor sales office. 11
Doc. No. MD-1091 Rev. R
(c) 2008 SCILLC. All rights reserved Characteristics subject to change without notice
CAT93C86 (Rev. C) REVISION HISTORY
Date Rev. Comments New Data Sheet Created From CAT93C46/56/57/66/86. Parts CAT93C56, CAT93C56, CAT93C57, CAT93C66, CAT93C76 and CAT93C86 have been separated into single data sheets Add Die Revision ID Letter Update Features Update Description Update Pin Condition Add Functional Diagram Update Pin Function Update D.C. Operating Characteristics Update Pin Capacitance Update Instruction Set Update Device Operation Update Ordering Information Added TDFN Package pin out Minor changes Update Features Update Pin Configuration Update Pin Functions Update D.C. Operating Characteristics (VCC Range) Update A.C. Characteristics (VCC Range) Update Ordering Information Update Package Outline Drawings Add Top Mark Code Link Update Document Layout Change logo and fine print to ON Semiconductor
14-May-04
L
10-Aug-04 03-Sep-04
M N
13-Oct-06
O
21-May-08 29-Oct-08
P R
Doc. No. MD-1091 Rev. R
12
(c) 2008 SCILLC. All rights reserved Characteristics subject to change without notice
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center: Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative

▲Up To Search▲

Price & Availability of CAT93C86LAT2C

	To Download CAT93C86LAT2C Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .